1. Field of the Invention
The present invention relates to a memory access apparatus.
2. Description of the Related Art
A processing circuit such as a DSP (Digital Signal Processor), in some cases, incorporates a plurality of memories for performing data processing at a high speed. For example, the DSP disclosed in Japanese Patent Application Laid-Open Publication No. 2006-190389 is equipped with two memories for storing data and has two sets of address bus and data bus provided for enabling simultaneous access to these two memories. Such a DSP realizes a speed-up of arithmetic processing, for example, by simultaneously reading out from the two memories by way of two buses two pieces of data to be input to a multiply accumulator (MAC).
A conceivable technique to achieve a further speed-up of the arithmetic processing in the DSP is providing a plurality of multiply accumulators. However, even if two multiply accumulators are provided, for example, in the DSP capable of simultaneously reading out two pieces of data as described above, it is only two pieces of data that can be simultaneously read out from the memories. For this reason, even if simultaneous arithmetic operations at these two multiply accumulators are attempted, reading out of the data to be input into one multiply accumulator can be performed only after completion of reading out of the data to be input into the other multiply accumulator and the speed-up of the arithmetic processing in the DSP can not be effectively achieved.